1. Field of the Invention
The present invention relates to electronic circuits and in particular to electric noise suppression circuits.
2. Description of the Related Art
As engineers seek ever increasing speeds in very large scale integration (VLSI) chips, complex problems continue to rise to the forefront. For example, as process feature sizes continue to shrink, metallurgical limitations are continually raising line-to-line interconnect coupling effects. These effects lead to increased concern over signal noise and noise tolerance. Design engineers continually fight and solve problems relating to signal noise.
Signal noise can take several forms. Due to coupling effects, signals can bounce in one or more of four distinct directions: above the ground, below the supply, below the ground, and above the supply. Of these directions, two may cause errors in circuit operations. Above-ground and below-supply signal noise can cause false switching events if the coupling effects causes the voltage level of a signal to cross the switching threshold of a given destination circuit. Below-ground signal noise and above-supply signal noise can cause a loss of state in certain types of large circuits.
To solve above-ground and below-supply noise problems, circuits have been employed to suppress this type of noise by adding transistors to the overall system. This solution works well as long as space or circuit density on a chip is not a concern. As chips increase in size, speed, and complexity, a larger emphasis occurs on designing compact circuits with a minor impact on chip density.
Currently available noise suppression circuits provide desired type of noise suppression. These circuits, however, require a significant area on the chip to include this type of circuit. This increased use in area can be difficult in applications in which adding circuitry is costly or prohibited.
Therefore, it would be advantageous to provide an above-ground and below-supply noise suppression circuit that can reduce noise effects.